1. Field of the Invention
The invention relates to a method of planarizing an integrated circuit device, and more particularly, to a method of planarizing a submicron integrated circuit device, 0.5 microns and below, by purposefully forming an oxide overlying the metal layer for etchback purposes.
2. Description of the Prior Art
In conventional planarization of the metallurgy-dielectric layers of an integrated circuit, a metal is deposited and patterned by conventional lithography and etching techniques. Then the dielectric layer, which is typically silicon oxide material, is formed thereover. Often, a spin-on-glass material is applied, baked, and cured. The spin-on-glass and dielectric layers may now be etched back to planarize the metallurgy-dielectric layers, followed by a second oxide deposition. There are basic problems in the choice of thickness of the dielectric/spin-on-glass layers. The problems occur particularly where there are both wide spaces, greater than 0.6 microns, and narrow spaces, less than 0.6 microns. For example, in the areas where contact is planned to be made to the patterned metal, it is desired to have a thick dielectric layer to keep planarity, but the thick dielectric will cause voids in other areas. Referring to FIG. 1A, there is shown a portion of a partially completed integrated circuit in which device structures 12 have been formed on a semiconductor substrate 10. A thick dielectric layer 14 has been covered by a spin-on-glass layer 16. Dotted line 18 illustrates the profile of the integrated circuit after the spin-on-glass etchback Note that void 19 has been formed. Alternatively, if a thin dielectric layer is used, there is lost planarity in the contact area and etchback encroachment of the metal pattern, but there will not be a void problem in other surface areas of the integrated circuit. This is illustrated by the partially completed integrated circuit in FIG. 1B which is identical to that shown in FIG. 1A except that the dielectric layer 14 is thin and the resulting profile 18 after spin-on-glass etchback shows a loss of planarity.
A number of patents have addressed these and other problems in planarization. Co-pending U.S. patent application Ser. No. 07/941,161 filed on Sep. 3, 1992 to "Spin-On-Glass Integration Process" by K. C. Chen and S. T. Hsia describes an integration of a partial etchback siloxane spin-on-glass process with a silicate spin-on-glass process. Co-pending U.S. patent application Ser. No. 07/957,801 filed on Oct. 8, 1992 to "Inter-Metal Dielectric Planarization Process" by K. C. Chen and S. T. Hsia describes an integration of a plasma-enhanced silicon oxide deposition, a TEOS with ozone silicon oxide deposition, and a spin-on-glass deposition process. U.S. Pat. No. 5,003,062 to Yen involves a sandwich process in which the spin-on-glass material can be either silicate or siloxane. A vacuum degassing step is used. In U.S. Pat. No. 4,775,550 to Chu et al, the first insulating layer is very thick, on the order of 8000 to 10,000 Angstroms. This thickness causes voids in the submicron area. The aforementioned patent to Chu et al as well as U.S. Pat. Nos. 4,676,867 to Elkins et al and 4,885,262 to Ting et al each show spin-on-glass etchback processes with use of a sandwich dielectric. A satisfactory solution to the planarization problem must still be found for the 0.5 micron and below generation.